Integrated Circuit (IC) fabrication generally begins by forming a number of semiconductor devices on a substrate, The semiconductor devices are next connected by a patterned conductor layer such as a metal layer. The semiconductor devices and metal layers are then covered by dielectric materials such as silicon dioxide and glass. Vias are etched to expose portions of the previous metal layers and new layers of metal and dielectric materials are deposited. This layering process continues until the IC is complete. IC fabrication is an area of considerable interest to the electronics industry because as fabrication techniques improve so do yield and device density.
Well known techniques currently provide methods for depositing IC materials layer by layer onto a substrate. Examples are Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD) and sputtering. CVD and PECVD provide for a material to be transported as a vapor to a surface and deposited thereon. Another example is spinning which involves placing an excess of material at a location on a surface and rotating the surface to distribute the material.
FIG. 1 depicts a cross section of a prior art IC 1 at an intermediate fabrication step. IC 1 is formed by taking a substrate 2 and depositing a patterned metal layer 3 connecting semiconductor devices on the substrate. The height of the patterned metal layer 3 results in an uneven topography. An oxide layer 4 is then deposited over the substrate 2 and the metal layer 3. The oxide is typically a tetra-ethyl-ortho-silicate (TEOS)-based oxide deposited using CVD or PECVD. This oxide layer is quite conformal to the underlying layers and thus forms hills in regions having metal thereunder and valleys in regions having no metal thereunder. This is simply a result of the underlying uneven topography. A thick spin-on-glass (SOG) layer 5 is then spun over the oxide layer to even out the topography.
The resulting IC 1 has a thick and reasonably planar surface layer of SOG 5. This surface must be etched back to remove all the SOG over the oxide layer hills prior to etching vias through the oxide to the underlying metal, thus permitting a future metal deposition to fill the via and contact the underlying metal. The reason for exposing the oxide layer hills is to avoid etching future vias through the SOG layer because SOG has poor stability. The etchback procedure is performed using plasma etching that is intended to cause the SOG and the oxide hills to be etched back at approximately the same rate. Etchback is a process known in the art and is performed using compounds such as CHF.sub.3, CF.sub.4, C.sub.2 F.sub.6, SF.sub.6 and combinations (i.e., mixtures) thereof.
Referring to FIG. 1, the desired etchback level is D. When the SOG layer and the oxide layer hills are etched back to level D, optimum IC characteristics are achieved. These characteristics include strong via construction, good planarization, no exposure of underlying metal during etchback, and controlled impedance between metal layers. If the SOG layer is etched back only to level D' there will be excess SOG present and the hills of the oxide layer will not be exposed. This will result in poor reliability of any vias that are etched down to the metal layer. If the SOG layer and oxide layer hills are etched back to level D" the metal will be exposed. This will result in poor device reliability, poor impedance control and low IC yield.
A problem with current etch techniques is control of the etch rate. When the SOG layer is etched back and the hills of the oxide layer become exposed, oxygen is liberated from the oxide layer. Oxygen liberation occurs as a result of an interaction between the etch chemistry and the oxide layer. When the SOG layer is exposed to this liberated oxygen, the SOG layer etches faster than the oxide layer. The SOG layer etch rates are increased by as much as 100% due to the oxygen. The result is an uneven surface with too much SOG etched back.
Techniques have been developed for compensating for the oxygen accelerated etch of SOG. It is known in the prior art that making the etch rate for the TEOS-based oxide layer 4 about twice the etch rate for the SOG layer 5 can compensate for these etch effects. In practice, a typical etch rate for SOG might be 50 .ANG./second, whereas the etch rate for TEOS-based oxide is about 100 .ANG./second. However, as the oxide hill becomes exposed and oxygen is liberated, the SOG etch rate increases to about 100 .ANG./second. The result is that when the oxide hill is exposed, both the SOG and the oxide materials then etch at about the same rate. This compensation technique is not a solution to the etch rate effect problem but rather an adjustment for it.
FIG. 2 depicts a prior art IC 1 after etchback. The SOG layer surface 5 is uneven. Particularly, the SOG layer surface is lower in regions adjacent to oxide layer 4 hills due to the liberation of oxygen during etchback. In other words, the released oxygen accelerates SOG etching most near the sites where the oxygen is released. This phenomenon is known as "loading" or "microloading" to those skilled in the art. This phenomenon occurs even though the compensation techniques described above can minimize it.
The uneven planarization depicted in FIG. 2 creates an increasing problem as the demand for device density increases. For example, when the distance between metal traces is large, resulting in large distances between oxide hills, an acceptable planarization can be accomplished with current techniques discussed above. However, when the distance between metal traces is small, resulting in small distances between oxide hills, there is a tendency for too much of the SOG to be etched away thereby leaving a vacant valley between the oxide hills. The vacant valley causes additionally deposited materials to exhibit a similar valley located over the same region.
What is needed is a method of etching back layers of IC materials at a consistent rate. By etching back the different materials at a consistent rate, superior planarity is achieved. A planar surface directly promotes higher yield and permits greater device density.
The present invention provides such a method.